Not All FPGAs Need to Be Discrete

Nvidia Unifies AI Compute with “Ampere” GPU

Tachyum Starts from Scratch to Etch a Universal Processor

Marvell Cranks Up Cores and Clocks with “Triton” ThunderX3

The Metronomic Cadence of Chippery from AMD

Minimalist Hyperscale Servers for the Rest of Us

AMD Is Determined to Gets Its Rightful Datacenter Share

Dennard Scaling Demise Puts Permanent Dent in Supercomputing (2019)

Point to Point in the Datacenter with Andy Bechtolsheim

A Deep Dive into AMD’s Rome Epyc Architecture

Rome Is the Fulcrum of AMD’s Datacenter Pivot

IBM is open sourcing the Power instruction set architecture

Intel Prepares to Graft Google’s Bfloat16 onto Processors

Better Than Floating Point?

Nvidia Makes Arm a Peer to x86 and Power for GPU Acceleration

Relentless Competition Drives Down Ethernet Switch Costs

Running TensorFlow at Petascale and Beyond

The Era of General Purpose Computers Is Ending

The Vital Engines of Commerce

Intel Unfolds Roadmaps for Future CPUs and GPUs

Intel Doubles Down on Doubled Up Xeons for HPC

Turning the CPU-GPU Hybrid System on Its Head

OpenMP Reaches Into The Parallel Universe Of GPUs

Teasing Out the Bang for the Buck of Inference Engines

Inferring the Future of FPGAs

Berkeley Lab Building Own Open Architecture Quantum Chips

Quantum Computers Are the Future Nukes of the IT World

First Wave of Spiking Neural Network Hardware Hits

FPGA Maker Snaps Up Deep Learning Chip Startup

Efficiency Gains of Optical Interconnects at Exascale

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