eMMC Failed. Why?

Device Clock Generation (2025)

Chasing resets

The FPGA Designer Who Didn't Get the Job

Fixing Xilinx's Broken AXI-lite Design in VHDL

Lessons in Hardware Reuse

Verilog Beginner's Tutorial

An Open Source Pipelined FFT Generator

About the ZipCPU

Lists of Posts Formally Verifying Various Hardware Blocks

Aggregating verified modules together

Building a prefetch module

My first experience with Formal Methods

Clocks for Software Engineers

Rules for new FPGA designers

Minimizing FPGA Resource Utilization