IBM Power – What's Next?

Turning Off Zen 4's Op Cache for Curiosity and Giggles

AMD Disables Zen 4's Loop Buffer

Pushing AMD's Infinity Fabric to Its Limit

Pushing AMD's Infinity Fabric to Its Limits

Broadwell's EDRAM: VCache Before VCache Was Cool

AMD's Turin: 5th Gen EPYC Launched

Skymont: Intel’s E-Cores reach for the Sky

Lunar Lake's iGPU: Debut of Intel's Xe2 Architecture

An Interview with Intel's Arik Gihon about Lunar Lake at Hot Chips 2024

Intel's Redwood Cove: Baby Steps Are Still Steps

Lion Cove: Intel's P-Core Roars

Telum II at Hot Chips 2024: Mainframe with a Unique Caching Strategy

Running Spec CPU2017 at Chips and Cheese?

Tesla’s TTPoE at Hot Chips 2024: Replacing TCP for Low Latency Applications

Qualcomm Oryon CPU Core Design

AmpereOne at Hot Chips 2024: Maximizing Density

AMD's Radeon 890M: Strix Point's Bigger iGPU

ARM or x86? ISA Doesn't Matter (2021)

AMD's Strix Point: Zen 5 Hits Mobile

Grace Hopper, Nvidia's Halfway APU

Cortex A73's Not-So-Infinite Reordering Capacity

Zen 5's 2-ahead branch predictor: how a 30 year old idea allows for new tricks

A Video Interview with Mike Clark, Chief Architect of Zen at AMD

Qualcomm's Oryon core: A long time in the making

Arm's Neoverse V2, in AWS's Graviton 4

The Snapdragon X Elite's Adreno iGPU

Examining the Nintendo Switch (Tegra X1) Video Engine

Testing AMD's Giant MI300X

Testing AMD's Bergamo: Zen 4c

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