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AMD's Magny Cours and HyperTransport Interconnect

Intel's Lion Cove P-Core and Gaming Workloads

Blackwell: Nvidia's GPU

Blackwell: Nvidia's GPU

Van Gogh, AMD's Steam Deck APU (2023)

AMD's CDNA 4 Architecture Announcement

AMD's Freshly-Baked MI350: An Interview with the Chief Architect

AMD's Pre-Zen Interconnect: Testing Trinity's Northbridge

Arm's Bifrost Architecture and the Mali-G52

Telum II at Hot Chips 2024: Mainframe with a Unique Caching Strategy

Zhaoxin's KX-7000

Dynamic Register Allocation on AMD's RDNA 4 GPU Architecture

RDNA 4's “Out-of-Order” Memory Accesses

An Interview with Oxide's Bryan Cantrill

Looking Ahead at Intel's Xe3 GPU Architecture

AMD's Strix Halo under the hood

Raytracing on Intel's Arc B580

Zen 5's AVX-512 Frequency Behavior

Alibaba/T-HEAD's Xuantie C910

Intel's Battlemage Architecture

SiFive's P550 Microarchitecture

The AMD Radeon Instinct MI300A's Giant Memory Subsystem

Disabling Zen 5's Op Cache and Exploring Its Clustered Decoder

Skymont: Intel's E-Cores reach for the Sky

Fujitsu's Monaka CPU: ARMv9, SVE2, and 3D Stacking

An EPYC Exclusive for Azure: AMD's MI300C – By George Cozma

IBM Power – What's Next?

Turning Off Zen 4's Op Cache for Curiosity and Giggles

AMD Disables Zen 4's Loop Buffer

Pushing AMD's Infinity Fabric to Its Limit

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