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Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V

CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions

ESP32-S31: Dual-Core RISC-V SoC with Wi-Fi 6, Bluetooth 5.4, and Advanced HMI

QRV Operating System: QNX on RISC-V

RVA23 Ends Speculation's Monopoly in RISC-V CPUs

The RISE RISC-V Runners: free, native RISC-V CI on GitHub

octopos: xv6 based operating system for risc-v in rust

Refinement Modeling and Verification of RISC-V Assembly Using Knuckledragger

My First Rust project: A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)

RISC-V Is Sloooow

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)

OpenTTD for Windows NT RISC

RISC-V simulator in Rust TUI you can now write Rust, compile, and run it inside step by step

A Verilog to Factorio compiler and simulator (working RISC-V CPU)

Running RISC-V in a VM to test my snaps

RISC-V Vector Primer

Emuko: Fast RISC-V emulator written in Rust, boots Linux

embassy-neorv32: Embassy on the NEORV32, an open-source RISC-V SoC

Milk-V Titan: A $329 8-Core 64-bit RISC-V mini-ITX board with PCIe Gen4x16

Box64 Expands into RISC-V and LoongArch territory

Closing the LLVM RISC-V gap to GCC, part 2: Probability and profitability

A glimpse into V8 development for RISC-V

Bare metal programming with RISC-V guide (2023)

T2/Linux Brings a Flagship KDE Plasma Linux Desktop to RISC-V and ARM64

Linux Runs on Raspberry Pi RP2350's Hazard3 RISC-V Cores (2024)

NeXTSTEP on Pa-RISC

Qualcomm acquires RISC-V focused Ventana Micro Systems

Qualcomm Acquires RISC-V Chip Designer Ventana Micro Systems

Arm stock tanks post Qualcomm's RISC-V acquisition of Ventana

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