progscrape: risc

European RISC-V Industrial Computing Initiative

9 days ago erici.eu risc

Building an OOO RISC-V CPU from scratch

5 days ago prawns.dev risc

India targets creating homegrown GPUs within 2 years and plans to commercialize indigenous SHAKTI and VEGA RISC-V processors — sees AI boom as a potential repeat of the Y2K opportunity for its IT industry

6 days ago tomshardware.com ai risc

Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5

13 days ago divagr.com ai risc

AI agent designs a complete RISC-V CPU from a 219-word spec sheet in 12 hours

34 days ago tomshardware.com ai risc

Extending concurrent separation logic to the hardware level to verify the xv6 OS kernel on RISC-V with AI agents

20 days ago arxiv.org ai ai-tooling compsci formalmethods kernel risc unix

Show HN: Our space game has a built-in RISC-V emulator that runs Linux

40 days ago againstallodds.games game linux risc show virtualization

Show HN: Our space game has a built-in RISC-V emulator that runs Linux

40 days ago againstallodds.games game linux risc show

RISC-V interpreter from the future

2 months ago abundance.build assembly risc rust

RISC-V Emulator and Linux System from Scratch

2 months ago github.com linux risc

Every Nvidia GPU has 10 to 30 RISC-V cores inside it

52 days ago xda-developers.com gpu nvidia risc

RISC-V is now officially supported by CPython

2 months ago blog.python.org risc

Diary of a writing RISC-V assembler

2 months ago thedevbirb.github.io assembler compiler risc

Hot Chips 2026: CUDA Targets RISC-V – By Chester Lam

2 months ago chipsandcheese.com hardware risc

A third world engineer responds to “RISC-V: They should have known better”

2 months ago rvembedded.com a11y culture hardware risc

The Alpha 21264 CPU: NT's Greatest RISC (1998)

3 months ago halfhill.com risc

Twenty Years of RISC OS Open

3 months ago riscosopen.org osdev risc

RISC-V: They should have known better

2 months ago dmitry.gr assembly compiler rant risc

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

2 months ago wccftech.com hardware risc

Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

3 months ago github.com risc show

Comu Fits a 144MHz CH32V203 RISC-V Board Inside a USB-A Port

3 months ago linuxgizmos.com hardware risc

Espressif releases Linux BSP for ESP32-S31 RISC-V boards

2 months ago cnx-software.com hardware linux release risc

Building a RISC-V emulator that boots in a browser via Wasm

3 months ago writethat.blog risc wasm

RISC-V Is Inevitable: State of the Union Keynote Argues

3 months ago eetimes.com risc

SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor

3 months ago arxiv.org risc

Charting RISC-V's Future in HPC

3 months ago hpcwire.com risc

Pushing the limits of RISC-V emulation

3 months ago shuklaayu.sh compiler risc

Pushing the limits of RISC-V emulation

3 months ago shuklaayu.sh compiler risc

Book: RISC-V System-on-Chip Design

4 months ago amazon.com risc

A Quine (self-replicating) Program in RISC-V Machine Language

3 months ago i.redd.it compiler risc

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European RISC-V Industrial Computing Initiative

Building an OOO RISC-V CPU from scratch

India targets creating homegrown GPUs within 2 years and plans to commercialize indigenous SHAKTI and VEGA RISC-V processors — sees AI boom as a potential repeat of the Y2K opportunity for its IT industry

Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5

AI agent designs a complete RISC-V CPU from a 219-word spec sheet in 12 hours

Extending concurrent separation logic to the hardware level to verify the xv6 OS kernel on RISC-V with AI agents

Show HN: Our space game has a built-in RISC-V emulator that runs Linux

Show HN: Our space game has a built-in RISC-V emulator that runs Linux

RISC-V interpreter from the future

RISC-V Emulator and Linux System from Scratch

Every Nvidia GPU has 10 to 30 RISC-V cores inside it

RISC-V is now officially supported by CPython

Diary of a writing RISC-V assembler

Hot Chips 2026: CUDA Targets RISC-V – By Chester Lam

A third world engineer responds to “RISC-V: They should have known better”

The Alpha 21264 CPU: NT's Greatest RISC (1998)

Twenty Years of RISC OS Open

RISC-V: They should have known better

Alibaba's TSMC-Built 5nm RISC-V Chip, XuanTie C950, Now Runs Qwen-3.8 27B Model Natively, Unlocking Massive Vertical Integration Tailwinds

Show HN: A Project Oberon System version running on RISC-V instead of RISC-5

Comu Fits a 144MHz CH32V203 RISC-V Board Inside a USB-A Port

Espressif releases Linux BSP for ESP32-S31 RISC-V boards

Building a RISC-V emulator that boots in a browser via Wasm

RISC-V Is Inevitable: State of the Union Keynote Argues

SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor

Charting RISC-V's Future in HPC

Pushing the limits of RISC-V emulation

Pushing the limits of RISC-V emulation

Book: RISC-V System-on-Chip Design

A Quine (self-replicating) Program in RISC-V Machine Language