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IEDM 2022: Did We Just Witness the Death of SRAM?

Intel, SiFive Demo High-Performance RISC-V on Intel 4

Arm Introduces the Cortex-A715

Arm Unveils Next-Gen Flagship Core: Cortex-X3

Reincarnating the 6502 Using Flexible TFT Tech for IoT

Intel Unveils BonanzaMine, a Bitcoin Accelerator ASIC – WikiChip Fuse

Samsung-Esperanto Concept AI-SSD Prototype – WikiChip Fuse

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along the Way

Arm Introduces Its Confidential Compute Architecture

AMD 3D Stacks SRAM Bumplessly

Hot Chips 33: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2

Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

The x86 Advanced Matrix Extension Brings Matrix Ops, to Debut W Sapphire Rapid

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

Odin: Co-Packaging Next-Gen DC Switches and Accelerators with Silicon Photonics

TSMC Details 5 nm: Germanium pMOS

IBM doubles its 14nm EDRAM density, adds hundreds of megabytes of cache

TSMC Announces 2x Reticle CoWoS for Next-Gen 5nm HPC Applications

Intel Refreshes 2nd Gen Xeon Scalable, Slashes Prices

Intel Axes Nervana Just Two Months After Launch

ARM Launches Cortex M55 and Ethos-U55

AMD Launches New Entry-Level Mobile ‘Dali’ Processors – WikiChip Fuse

A Look at Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Designs

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

TSMC 5-Nanometer Update

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