Chinese startup launching RISC-V laptop for devs and engineers priced at around $300

RISC-V Now Supports Rust In the Linux Kernel

Muse Book laptop features SpacemiT K1 octa-core RISC-V AI processor, up to 16GB RAM

Supporting RISC-V Performance Counters for Linux Perf (2021)

IR for WASM and RISC-V

SOAR-ing Away with Smalltalk: Berkeley RISC-III

RISC-V support in Android just got a big setback

Why RISC-V is so important

US investigates China's access to RISC-V — open standard instruction set may become new site of US-China chip war

Implementing Neural Networks on a "10-cent" RISC-V MCU

Making an RISC-V OS (Part 3): Managing free memory

SiFive Premier P550 RISC-V development board

America's Commerce Department is Reviewing China's Use of RISC-V Chips

How to improve the RISC-V specification

Vortex: OpenCL compatible RISC-V GPGPU

RISC OS 5.30 now available

US Government reportedly ponders crimping China's use of RISC-V

Is Rivos Building an RISC-V AI Chip?

Rust Custom Target for QEMU RISC-V on Apache NuttX RTOS

Imagination licenses RISC-V CPU cores for smart TVs, IoT, embedded stuff

New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously

Get Started with Embedded Swift on ARM and RISC-V Microcontrollers

Alibaba promises server-class RISC-V processor in 2024

Efinix Titanium Ti375 FPGA offers quad-core hardened RISC-V, PCIe Gen 4, 10GbE

Tenstorrent unveils Grayskull, its RISC-V answer to GPUs

Scaleway launches RISC-V servers

Factorio Yosys: a full yosys backend for factorio that can compile a riscv core

The Race to 2nm: RISC-V Chips in Japan – By Dr. Ian Cutress

Optimize sgemm on RISC-V platform

DeepComputing ROMA RISC-V Laptop

More →